In electronic systems, subsystem building blocks are frequently implemented in separate integrated circuit devices. To communicate with one another, the building blocks have I/O pads interconnected with one another. In the evolution of integrated circuit fabrication processes, the operating voltages have progressively diminished. In interconnecting subsystem building blocks, integrated circuit devices operating at different supply voltages will be connected by their I/O pads. Across the interconnects of the various integrated circuit devices various combinations of voltages will interact as high logic level signals are communicated.
Generally there is no problem for a device with a lower supply voltage driving a device operating from a higher supply voltage. Additionally, there is typically no problem with the higher supply voltage level being applied to a tristated pulldown only device in the lower supply voltage realm. A problem arises in a CMOS integrated circuit technology when a tristated PMOS pullup device in a low supply voltage realm is driven to a high logic level by a device in a high supply voltage realm.
With reference to FIG. 1, a 3 volt (V) realm 103 connects to a 5 V realm 105 in a schematic diagram of a prior art interconnect network 100 with mixed supply voltages. A 3 V output pullup device 112 connects between a 3 V supply 113, a 3 V input 111, and a 3 V I/O pad 133. A source-substrate diode 116 and a drain-substrate diode 117 connect in parallel from the source and drain respectively of the 3 V output pullup device 112 to a 3 V pullup substrate node 119. A source-substrate connection 118 connects between the 3 V pullup substrate node 119 and the 3 V supply 113. A 3 V output pulldown device 114 connects between the 3 V input 111, the 3 V output pullup device 112, the 3 V I/O pad 133, and ground.
A 3 V input pullup device 122 connects between a 3 V output 121, the 3 V supply 113, and the 3 V I/O pad 133. A 3 V input pulldown device 124 connects between the 3 volt output 121, the 3 V input pullup device 122, the 3 V I/O pad 133, and ground.
A 5 V output pullup device 132 connects between a 5 V supply 115, a 5 V input 131, and a 5 V I/O pad 135. A 5 V output pulldown device 134 connects between the 5 V input 131, the 5 V output pullup device 132, the 5 V I/O pad 135, and ground.
A 5 V input pullup device 142 connects between a 5 V output 141, the 5 V supply 115, and the 5 V I/O pad 135. A 5 V input pulldown device 144 connects between the 5 V output 141, the 5 V input pullup device 142, the 5 V I/O pad 135, and ground.
The output of the 3 V output pullup device 112, when tristated, presents a p-n diode connection, in the form of the drain-substrate diode 117, from an output drain diffusion to substrate. Even though the 3 V output pullup device 112, is a tristated PMOS FET, the high logic level from the 5 V realm 105 will conduct through the diode and cause high current and possibly latchup conditions that may damage the 3 V realm 103 device.
In an effort to solve problems with high input bias levels applied to input diffusions and substrates, previous port drivers have incorporated complex networks for switching substrate biasing to protective voltage levels. What is needed is a port driver operating in a low-voltage realm that is tolerant of high voltages applied from external system devices without a burden of incorporating complex networking for switching the biasing of the substrate. Additionally, such a low-voltage realm port driver ideally drives a high logic level output to the full supply level of the indigenous voltage realm.